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Eureka Technology designed high-performance memory controller supports DDR2 and DDR3

Design Engineers at Intellectual Property (IP) Company Eureka Technology Build DDR3 SDRAM Controller for High-Performance ASIC / SoC Applications.

The development reveals the advantages of DDR3 over previous generations of SDRAM, resulting in significantly increased bandwidth and improved power consumption. The controller implements fast page access, pipelining and “smart” arbitration of requests. With support for both DDR3 and DDR2, SoCs and CIs can seamlessly transition from one type of SDRAM to another. At the same time, the high degree of programmability of the IP-core provides a reserve for modernization in view of future development.

DDR3 controller core is already available for licensing. According to the developer, its implementation can be synthesized for almost any ASIC and FPGA. Integration with other components is facilitated by the standard DFI PHY interface. Optionally, you can add support for AXI, AHB and others interfaces, configure the controller to work with one or more ports.

Source: Eureka Technology

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