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Intel: Built-in 2T-DRAM Memory Will Dramatically Improve Processor Performance

Last week’s Research @ Intel Day
Intel talked about a technology that might,
will significantly increase the productivity of future generations
processors.

As you know, it is determined by factors such as length
pipelines, the number of cores, their frequency and the amount of cache memory. Still not worth it
forget about the exchange of data between processor cores. So, for example, at 65nm
Kentsfield bandwidth is only 8-9 GB / s, and
in 45nm Harpertown chips – already 18-20 GB / s.

It is due to the internal bandwidth that it is planned
to raise the computing power of Intel processors. Small
the company’s research team has recently been leading the development of technology,
which would allow, due to DRAM-memory, to speed up the exchange
data inside a processor with multiple cores. They managed to reduce the size of the cells
DRAM to just a couple of transistors and get rid of it completely
containers. These two steps should become fundamental to the new technology.
Probably static memory, complex and expensive, will subsequently be completely
replaced in processors with dynamic.

Unlike newer DRAM requiring 2 transistors to store 1 bit of data,
SRAM has more “consumption” – 6 transistors, and memory 1T-SRAM
not used in these applications. However, power consumption
SRAM is slightly lower than DRAM, but it costs more.

According to the company, its engineers managed to obtain working samples
2T-DRAM memory, manufactured at 65 nm and clocked at 2 GHz.
Bandwidth – impressive 128 GB / s. Accordingly, if you find a way
raise the frequency to the level of top-class processors (QX9770 / 9775), then this value
would increase to 204.8 GB / s. This is about 10 times more efficient solution,
than using today’s L2 cache. Moreover, such an approach would completely
changed the programming for these processors.

It is expected that thanks to 45nm
Intel High-k technology will be able to catch up in frequency
processors and the next logical step could
Become integrating DRAM memory cells into Intel processors
Terascale, which will use many x86 cores.

When reducing cache memory problems to almost zero (with low-latency
internal memory with a bandwidth of about 200 GB / s) the main task
using the potential of such processors will subsequently be entrusted to
programmers.

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