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Elpida managed to reduce DRAM chips by 20% without changing the technical process

The largest Japanese DRAM manufacturer announced the completion of the development of a “compressed” version of 1-Gbit DDR2 SDRAM chips. The reduction in size allowed a 20% increase in the number of chips obtained from one 300-mm plate. Serial production of the new memory should begin before the end of the year at the facilities of Elpida Memory itself in Hiroshima; a Taiwanese facility owned by Elpida’s joint venture Rexchip; and in the factories of the PSC company.

Reducing the size of chips made possible by the use of a new architecture in 65nm products of the first generation. For production, a technical process is used, which has already demonstrated high productivity and a high percentage of product yield. According to Elpida, this will make the cost of “compressed” versions of products about 20% less than the cost of the first generation. What’s more, as the move to 50nm is driving up costs due to capital investment, Elpida is confident that the new 65nm chips will be able to compete on price with 50nm products announced by other DRAM manufacturers.

However, Elpida does not abandon the development of 50-nm technology. The corresponding technical process is in the final stage of development. According to the company, the work will be completed in November, and mass production will begin in late December. Thus, the company is slightly ahead of its own schedule, according to which the development of 50 nm norms was planned for the first quarter of 2021. The transition to a 50-nm process technology will have to further increase the performance of microcircuits and reduce their cost.

Source: Elpida Memory

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