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IDF: Gelsinger on Milliwatts and Petaflops Using Intel Atom, Larrabee, and Nehalem CPUs
In his keynote address, “Peta FLOPs from milliwatt,” Pat Gelsinger, Intel Senior Vice President
and general manager of the Digital Enterprise Group, noted that processors based on Intel architecture are now used in various devices – from MID to
HPC systems (High Performance Computing).
Workstations on Nehalem, design tasks (aerodynamic calculations)
Specifically, Intel Xeon processors became the basis for three of the five largest HPC systems in the world, with Intel shipped approximately four out of every five processors in the HPC market in 2021.
Gelsinger provided some technical data for the next generation of microarchitecture processors
Nehalem Commencement of Production in Q4. First of all, Nehalem processors will appear in the segment of high-performance desktop PCs and dual-processor server systems, in other market segments they will be presented in 2021.
Nehalem processors are designed to scale from two to eight cores. Gelsinger announced a new Intel Advanced Vector Extension instruction set that is slated to be supported from 2021 in the Sandy Bridge processor family following Nehalem.
In conclusion, Gelsinger spoke about the concept of Intel Visual Computing and the need to increase computing power
– in 10 years exaflops are already “promised” (which systems will have on
Intel CPU-based used in medicine and processing
images), and after another 10, the era of zetaflops (computers for tasks
researchers-geneticists, analysis of the Earth’s climate, etc.P.); expanding memory bandwidth and I / O subsystems, supporting improved graphics, improving software tools and libraries designed to provide photorealistic 3D rendering, support for high-definition audio and video, as well as computer modeling – all this will help to make the work on the computer more convenient.
Larrabee will be one of the critical elements in achieving these goals, which will use multiple Intel-based cores, a new architecture cache, and a new set of instructions for vector processing.